Referring to FIG. 1, a circuit (or phase locked loop (PLL)) 10 is shown illustrating a conventional scheme for clock recovery. The circuit 10 generally comprises a frequency detector 12, a phase detector 14, a multiplexor 16, a loop filter 18, a voltage controlled oscillator (VCO) 20, a frequency difference detector 21 and a buffer 22. The PLL 10 uses the frequency detector 12 and the frequency different detector 21 to ensure that the frequency of a signal presented by the VCO 20 is within a predetermined frequency range relative to an external reference signal (e.g., REFCLK) presented to the frequency detector 12. The frequency detector 12 generates pulses whose width is proportional to frequency difference of the incoming signals. The phase detector 14 ensures that the phase of the signal presented by the VCO 20 is aligned with an incoming data stream (e.g., DATA) presented to the phase detector 14. The frequency difference detector generates a control signal (e.g., LINKFAULT) indicating the status of the VCO frequency to the PLL compared to an external device (not shown). The signal to the external device is typically sent through a dedicated output pin connected to the buffer 22.
Referring to FIG. 2, a circuit 30 illustrating a conventional scheme for detecting the difference in frequencies between two clock signals is shown. The circuit 30 comprises a counter 32, a counter 34 and a compare block (or circuit) 36. The counter 32 counts the cycles of a reference clock signal (e.g., REFCLK). The counter 34 counts the cycles of a VCO clock signal (e.g., VCOCLK). The circuit 30 uses a signal START to initiate the VCO clock signal counter 34. The signal START may be generated periodically (i.e., once every certain number of cycles) to provide a periodic timing reference. The counter 32 tracks the number of VCO clock signal cycles to generate a count signal (e.g., via VCO_COUNT). The counter 34 counts the number of reference clock signal cycles to generate a count signal (e.g., via REF_COUNT). The compare circuit 36 compares the signal VCO_COUNT with the signal REF_COUNT to determine whether or not the VCO is presenting (or generating) a clock signal having a frequency within a predetermined window (i.e., within predetermined upper and lower boundaries, or a predetermined frequency range, relative to the reference clock signal REFCLK). The compare circuit 36 indicates that the VCO clock signal frequency is not within the predetermined window by presenting an active control signal (e.g., OutOfLock).
The circuit 30 gives rise to a problem in that an Out-of-lock signal (OOL) may be inadvertently or prematurely deactivated when the PLL pulls its output signal within the allowable predetermined frequency window, only to be reasserted a very short time later (typically less than 100 msec but at least one range compare cycle later; in one example, at least 50 μsec.) The inadvertent or premature deactivation of the signal OOL typically occurs as a result of jitter or noise or an artifact of the frequency-centering process. The signal OOL may “glitch” which may make designing a circuit board very difficult, particularly when the signal OOL appears at an I/O pin.